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doc.# dsfp - hv461 c071913 hv461 general description the hv461fg is a highly integrat ed ring generator controller ic, designed to work with a patented four-quadrant inverter topology, with synchronous rectifers on the secondary side to achieve higher effciencies. the inverter delivers the desired ring voltage from a standard -48v telecom power supply. the hv461 consists of a sine wave synthesizer that can provide eight different ring frequencies for universal applications. any other frequency in the 12 to 63hz range can be obtained by applying an external logic signal to the ic. a transparent latch permits control of the ringer output individually or through the 8-bit bus. the output amplitude and dc offset can be digitally controlled providing high fexibility to the designers. the patented inverter topology using the hv461 controller ic is capable of achieving higher effciencies, typically over 80%, and drive up to a 40 ren load. the controller allows ring generators to provide a foating 94vac (rms) waveform that can be referenced to either the -48v or any other offset level by using the programmable offset pins of the ic. output offset may be achieved by directly generating the offset within the power stage, or by foating the output stage on a dc source, or both. the hv461 also has an internal boost converter that can be used to provide the gate drive voltages for the two mosfets on the primary side and the two secondary rectifers on the secondary side. typical application circuit -48v -48v or 0v -48v 94va c (rms) +3.3v i/o current sense xtal vdd gate drive ou t hv461 features ? 3.3v operation, logic inputs 3.3v & 5.0v compatible ? digital control of ring frequency, amplitude, and offset ? control via 8-bit bus or via individual inputs ? 8 built-in ring frequencies: 12, 16 2 / 3 , 20, 25, 33 1 / 3 , 40, 50, 60hz ? external ring frequency input ? low distortion sine wave synthesizer ? ac-only, ac+dc, or dc-only ringer output ? adjustable over-current protection ? internal precision voltage references ? power-on reset and undervoltage lockout for hotswap capability ? sync output with adjustable lead time for synchronizing ringing relays ? fault output for problem detection ? open or closed loop operation ? effcient 4-quadrant operation ? zero-cross turn-on with zero-cross turn-off option applications ? pbx ? dlc ? key systems ? remote terminal ? wireless loop systems ring generator controller ic supertex inc. supertex inc. www .supertex.com
2 doc.# dsfp - hv461 c071913 hv461 absolute maximum ratings parameter value v dd +4.0v digital inputs -0.5v to +7.0v analog inputs -0.5v to +7.0v storage temperature -65c to +150c operating temperature -40c to +85c sym parameter min typ max units conditions electrical specifcations (unless otherwise specifed: v dd = 3.3v, t a = -40c to +85c) absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. pin confguration external supply sym parameter min typ max units conditions gate drive supply v dd supply voltage 3.0 3.3 3.6 v --- i dd supply current (av dd + dv dd ) - 7 30 ma f pwm = 100khz f osc = 19.6608mhz sw outputs nc open loop confg, external v gd v gd boost circuit voltage 9.0 9.6 10.2 v --- i gd gate drive supply current - - 5.0 10 ma ma v dd = 2.97 - 3.63v, sw outputs unloaded v dd = 2.50 - 2.93v, sw outputs unloaded v dr(lo) drive voltage, low - - 0.2 v i out = -10a v dr(hi) drive voltage, hi v dd - 0.4 - - v i out = 10a t rise rise time - - 100 ns c l = 200pf t fall fall time - - 100 ns c l = 200pf f gd converter frequency same as pwm --- d gd duty cycle 45 50 55 % --- 1 48 product marking 48-lead lqfp (top view) yy = year sealed ww = week sealed l = lot number c = country of origin* a = assembler id* = ?green? packaging *may be part of top marking top marking bottom marking yyww hv461fg lllllllll cccccccc aaa 48-lead lqfp package may or may not include the following marks: si or ordering information part number package option packing hv461fg-g 48-lead lqfp 250/tray hv461fg-g m931 48-lead lqfp 1000/reel typical thermal resistance package ja 48-lead lqfp 52 o c/w -g denotes a lead (pb)-free / rohs compliant package supertex inc. www .supertex.com
3 doc.# dsfp - hv461 c071913 hv461 sym parameter min typ max units conditions logic inputs sym parameter min typ max units conditions reset sym parameter min typ max units conditions undervoltage lockout sym parameter min typ max units conditions voltage reference v ref1 reference voltage 1 1.213 1.250 1.288 v t a = 25oc tc ref1 temperature coeffcient - 200 - v/oc --- ?v ref1 output regulation -6.25 - +6.25 mv i out = 100a v ref2 reference voltage 2 2.425 2.500 2.575 v t a = 25oc tc ref2 temperature coeffcient - 500 - v/oc --- ?v ref2 output regulation -12.5 - 0 mv i out = 0 - 100a source v in(lo) input voltage low - - 0.3v dd v --- v in(hi) input voltage high 0.7v dd - - v --- i in(lo) input current low - - -1 a v in = 0v i in(hi) input current high - - 1 a v in = 5.0v c in input capacitance - - 10 pf --- t s set-up time - - 100 ns --- t h hold time - - 100 ns --- v reset(on) reset on voltage 1.200 1.325 1.450 v --- v reset(off) reset off voltage 1.000 1.125 1.250 v --- v reset (hys) reset hysteresis 0.150 0.200 0.250 v --- i p-up reset pull-up current 7.0 10.0 13.0 a --- v dd(on) v dd on voltage 2.75 2.85 2.95 v --- v dd(off) v dd off voltage 2.50 - - v --- v dd(hys) v dd hysteresis - 0.10 - v --- v gd(on) v gd on voltage same as v gd regulation point v --- v gd(off) v gd off voltage 7.0 - - v --- v gd(hys) v gd hysteresis 0.20 - - v --- supertex inc. www .supertex.com
4 doc.# dsfp - hv461 c071913 hv461 sym parameter min typ max units conditions amplifers sym parameter min typ max units conditions sinewave synthesizer sym parameter min typ max units conditions fault output v out(lo) output voltage low - - 0.2 v i out = 1ma k fault(on) fault on threshold 6 8 10 %* c fault = 10f k fault(off) fault off threshold 1 2 3 %* c fault = 10f t fault(hold) fault hold time 50 - - ms c fault = 10f * percent of time pwm overrange or overcurrent is active. v in input range 0.25 - 2.50 v --- i in input bias current -500 - 500 na v in = 0.5v to v dd -0.5 v offset input offset voltage -15 - 15 mv --- v out(min) min output - 0.1 0.2 v i out = 100ua v out(max) max output v dd -0.2 v dd -0.1 - i out = 100ua a vol open loop gain 60 80 - db --- cmrr common mode rejection ratio -40 -60 - db --- gbw gain-bandwidth product 1.0 - - mhz --- sl slew rate 0.1 - - v/s --- psrr power supply rejection ratio -30 - - db f<10khz v dc dc level 1.213 1.250 1.288 v --- a amplitude 1.900 2.000 2.100 0 v p-p v p-p amp 00 amp = 00 f 0 frequency - 16 2 / 3 - hz freq = 000, f osc = 19.6608mhz f 1 frequency - 20 - hz freq = 001, f osc = 19.6608mhz f 2 frequency - 25 - hz freq = 010, f osc = 19.6608mhz f 3 frequency - 30 - hz freq = 011, f osc = 19.6608mhz f 4 frequency - 33 1 / 3 - hz freq = 100, f osc = 19.6608mhz f 5 frequency - 40 - hz freq = 101, f osc = 19.6608mhz f 6 frequency - 50 - hz freq = 110, f osc = 19.6608mhz f 7 frequency - 60 - hz freq = 111, f osc = 19.6608mhz ?f frequency accuracy - - 0.1 % f osc = 19.6608mhz thd harmonic distortion - - 3 % c sine = 33nf f ring = 16 2/3 to 60hz r out output resistance 14.4 72.0 16.0 80.0 17.6 88.0 k? k? amp 00 amp = 00 supertex inc. www .supertex.com
5 doc.# dsfp - hv461 c071913 hv461 sym parameter min typ max units conditions external ring frequency sym parameter min typ max units conditions enable and sync sym parameter min typ max units conditions sine reference attenuator sym parameter min typ max units conditions dc ref multiplexer f cap(lo) capture frequency low* - 12 - hz loop flter = (33f+10k?)||4.7f f cap(hi) capture frequency high* - 63 - hz loop flter = (33f+10k?)||4.7f v in(lo) input low - - 0.3 - v dd v --- v in(hi) input high 0.7v dd - - v --- ? ring phase jitter, sine ref out -5 - +5 deg loop flter = (33f+10k?)||4.7f * lock range is the same as capture range v dc dc level 1.213 1.250 1.288 v v in(dc) = 1.250v a off attenuation - - 0.010 v/v amp = 00 a lo attenuation 0.490 0.500 0.510 v/v amp = 01 a med attenuation 0.735 0.750 0.765 v/v amp = 10 a hi attenuation 0.980 1.000 1.020 v/v amp = 11 v in input range 0.2 - v dd - 0.2 v --- v in input range 0.0 - v dd v --- i in input bias current -500 - +500 na --- i off off leakage current - - 1.0 a v in = 0.5 to v dd - 0.5v v out(lo) sync output voltage low - - 0.2 v i out = 1.0ma sink v out(hi) sync output voltage high v dd - 0.2 - - v i out = 1.0ma source t on enable delay, on - - 5 s --- t off enable delay, off 0 - 60 1 s ring cycle syncmode = 0 syncmode = 1 sync(on) sync on lead time 4.5 5.0 5.5 ms c sine = 0 r sync = 154k? c sync = 47nf sync(off) sync off delay -250 0 +250 s c sine = 10nf t sync(rise) sync rise time - - 300 ns c l = 50pf t sync(fall) sync fall time - - 300 ns c l = 50pf supertex inc. www .supertex.com
6 doc.# dsfp - hv461 c071913 hv461 sym parameter min typ max units conditions pwm controller pwm frequency f pwm pwm frequency 21.25 127.5 25.00 150.0 28.75 172.5 khz khz r pwm = 500k? r pwm = 83k? t pwmsync(out) pwm sync output pulse width 30 50 70 ns --- t pwmsync(in) pwm sync input pulse width 25 - - ns --- f pwmsync(in) pwm sync input frequency range 25 - 150 khz --- v pwmsync(lo) pwm sync output low voltage - - 0.2 v i out = 1.0ma sink i pwmsync pwm sync pull-up current - 100 - a --- switch driver outputs v out(lo) output voltage, low - - 0.2 v i out = 20ma sink v out(hi) output voltage, high v gd -0.2 - - v i out = 20ma source t rise rise time - - 50 ns c l = 4nf t fall fall time - - 50 ns c l = 4nf timing d duty cycle 23 48 73 25 50 75 27 52 77 % % % pwm in = 0.625v pwm in = 1.250v pwm in = 1.875v v dcl = 0v d limit duty cycle limit 12 72 22 62 20 80 30 70 28 88 38 78 % % % % v dcl = 0.50v, pwm in = 0v v dcl = 0.50v, pwm in = 2.5v v dcl = 0.75v, pwm in = 0v v dcl = 0.75v, pwm in = 2.5v i dcl v dcl input current - - 1.0 a v dcl = 0 - 1.0v t db primary switch deadband 0 0.95 100 1.00 150 1.05 ns s c db = 0pf r db = 14k?, c db = 100pf t dly secondary switch delay 0 0.95 100 1.00 150 1.05 ns s c dly = 0pf r dly = 14k?, c dly = 100pf supertex inc. www .supertex.com
7 doc.# dsfp - hv461 c071913 hv461 sw1 t db sw2 sw3 sw4 t db t dly on off off on on off off on t dly figure 1: switch timing diagram figure 2: enable and sync timing - syncmode = 0 decay time dependant on value of cap connected to sine ref. enable sync sine ref erramp siezed siezed free t on sync(on) t off switch outputs enable amp off sw1 sw2 sw3 sw4 0 00 xx off off off off 0 00 xx off off switching switching 1 xx xx switching switching switching switching x = dont care, 00 = 01,10, or 11 supertex inc. www .supertex.com
8 doc.# dsfp - hv461 c071913 hv461 figure 4: amp timing figure 3: enable and sync timing - syncmode = 1 enable sync filtered sine ref sync at 0 o or 180 o erramp siezed siezed free t on(delay) sync(on) sync(off) sync t sync(delay) sync(on) sine ref amp amp = 00 amplitude changes sync?d to zero crossings amp 00 amp 00 amp = 00 typical application figures 5 and 6 on pages 9 and 10 show the schematic of a typical 15 ren ring generator application. the basic design equations for elements connected to different pins are given in the pin descriptions table beginning on page 11. supertex inc. www .supertex.com
9 doc.# dsfp - hv461 c071913 hv461 figure 5: block diagram and typical applicatin circuit v gd fault vref1 ringer output output reference sync v dd reset 3 c ref1-3 dcref osc sine wave synthesizer 2 freq 2 agnd dvdd reset sineref error amplifier boost converter syncmode enable control enable pwmsync rosc sw1 sw2 sw3 sw4 cl+ cl- clcomp sync fring vgd clk e l vdcl v ref pll vref2 precision reference v ref1 dgnd pwm controller pwmin enable pri deadband sec delay switch drivers current limit duty cycle limit osc freq amp offset sync tsync v ref1 v ref1 pgnd avdd xtal v dd vdr diffamp- pllflt tdb tdly v ref1 comp2 comp1 v ref freq0 freq1 freq2 amp0 amp1 off0 off1 enable +1 undervoltage detecto r undervoltage latch offset mux deglitcher cfault v dd v dd 2 +1 1.25v 2.50v t ran sp a re n t l a tc h refer to power stage schematic v dd r fault 100k v dd to host controller external rin g frequency c pll2 33f r pll 10k pll filter only require d for external ring frequency to host controlle r r dly 4.7k c dly 120p f c fault 10f r dcl1 100k r fb3 30.1k c comp2 1.0nf r comp 2.7k r dc1 r tsync 3.3k c tsync 100n f y1 19.6608mhz c reset 4.7f c ref2 100n f c dd1 10f l gd 330h d gd 4148 q gd tn2504 c gd 6.8f c sine 47nf c dc 100n f r tsync and c tsync selected fo r desired ring sync lead time. hv461 r dc1 - rdc4 selected fo r the desired dc offsets. v ref2 c ref1 100n f c dd2 100n f v dd r dc2 r dc3 r dc4 c comp1 47nf r fb4 4.02m r fb2 4.02m r fb3 30.1k diffamp+ ] refer to power stage schematic ] differentia l amplifier diffamp0 20k 10k 10k 20k 20k 20k 20k amplitude mux c pll1 4.7f [ 10a + overrange overcurren t c dly selected for desired fault response time r osc 267k r dcl2 33k r db 4.7k c db 120p f + + + + supertex inc. www .supertex.com
10 doc.# dsfp - hv461 c071913 hv461 figure 6: typical power stage for 15 ren ring generator -48v sw 2 sw 1 sw 3 sw 4 cl- cl+ clcomp pwr gnd v ref1 output reference ringer output q sw2 irf9540 c in1 470f t main 1:6.5:6.5 zsw2a,b 12v d sw2 mmbd4148 l in ferrite bead r cl4 6.8k t sw3 1:1 c cl2 68nf c cl1 10nf r cl3 39k r cl2 10k r cl1 10k r sense 0.18k r sw2b 100k r sw2a 220 c sw2 100nf c sw1 100nf zsw1a,b 12v d sw1 mmbd4148 r sw1b 100k r sw1a 220 c in2 470f c pri2 470nf c pri3 100 f c pri4 470nf c pri1 100 f r pri2 100k r pri1 100k 52h d sw4 mmbd4148 d sw3 mmbd4148 c sw3a 100nf q sw1 irf530 q sw4 irf320 q sw3 irf320 t sw4 1:1 c sw4a 100nf c sw4b 100nf r out1 1.0m r out2 1.0m c sw3b 100nf r sw3b 220 r sw3a 220 r sw4b 220 r sw4a 10k c out1 1.0f c out2 1.0f supertex inc. www .supertex.com
11 doc.# dsfp - hv461 c071913 hv461 pin name description 1 dcref3 see dcref1 and dcref2 (pins 47 & 48). 2 vref1 outputs a 1.25v nominal reference voltage. bypass with a 100nf capacitor to ground. 3 vref2 outputs a 2.50v nominal reference voltage. bypass with a 100nf capacitor to ground. 4 avdd supply for the analog section. 3.0 to 3.6v must be from the same source as dvdd. bypass with a 100nf capacitor to ground as close as possible to the ic. 5 tsync an rc network connected to this pin determines the sync pulse lead time (see sync pin 14). t lead = 0.48rc if sync is not utilized, tsync must still have a connected rc network. 6 xtal a crystal from this pin to ground provides the frequency reference for the internal sine wave synthesizer. a 19.6608mhz baud rate crystal provides the 8 most common ring frequencies. the crystal is operated in the series mode. a loading capacitor is not necessary. see also freq0C2 (pins 21C23) and fring (pin 7). 7 fring ring frequency is normally selected from the 8 built-in frequencies using control inputs freq0C 2. other arbitrary frequencies in the range of 12 to 63hz may be obtained by applying an external signal to fring. this external signal sets the ring frequency at a 1:1 ratio. the ring signal remains a sine wave, with amplitude and offset still controlled via ampx and offx. the ring signal, while frequency locked to the fring signal, is not phaseCsynchronized to it. this allows the ring signal to immediately start at 0o when enabled via enable or amp 00. when unused, this input must be connected to vgd. 8 pllflt phase locked loop flter. an rc network connected to this pin stabilizes the pll that locks on to the optional external ring frequency signal. (see fring, pin 7) the rc network determines the lock time of the pll. due to the low frequencies involved, it may take a couple seconds to lock to the external signal. see the typical application schematic for typical values. when unused, this pin should be left unconnected. 9 rosc a resistor from this pin to vdd sets the pwm frequency. f pwm 12.5ghz? / r osc (valid for 20- 150khz) 10 reset a capacitor from this pin to ground provides a powerCon reset interval. it has an internal 10a pullCup to charge the external reset capacitor. alternatively, an external logicClevel or openC drain signal may be applied to implement the reset function. during the reset interval when v reset <1.325v, the ringer output is disabled regardless of the state of the enable input, allowing time for the host controller to assume control. use a low leakage tantalum or ceramic capacitor . t reset = 1.325v c reset / 10a 11 pwmsync this pin functions as both an input and an output. it is openCdrain with an internal 100a pull- up. as an output, it provides a short, low-going pulse at the internal pwm frequency. as an input, it synchronizes internal pwm frequency to the externally applied signal, provided the external signal is at a higher frequency. the low-going applied sync pulse should be between 25ns and less than the pwm period in duration. the external source should be open drain. if the pwmsync pins of multiple hv461s are tied together, their pwm frequencies will be phase- locked to the hv461 with the highest free-running frequency. a maximum of 10 hv461s may be tied together. if unused, this pin should be left unconnected. 12 cfault a capacitor from this pin to ground sets the integration time of the fault detection circuitry. a larger capacitor provides less suseptability to transient problems, while a smaller capacitor provides quicker response. values in the range of 1f to 100f are appropriate. if the fault output is not used, this pin should be grounded. see also fault (pin 15). pin description (refer to pin confguration on page 2) supertex inc. www .supertex.com
12 doc.# dsfp - hv461 c071913 hv461 pin name description 13 syncmode with syncmode low, ringer output ceases the instant enable goes low. when high, ringer output ceases at the next ring signal phase crossing (0o/180o) after enable goes low . 14 sync outputs a pulse indicating sine reference 0o and 180o phase crossing (not to be confused with zeroCvoltage crossing). the rising edge precedes phase crossing by a userCadjustable time period (see tsync pin 44). falling edge coincides with sine reference phase crossing. sync is digitally derived, therefore phase shifts caused by the external flter capacitor at sineref will not be refected at the sync output. 15 fault indicates abnormal operating conditions of output overcurrent, supply undervoltage (vdd & vgd), or pwm overrange (duty cycle limit C see vdcl, pin 3). together, these 3 conditions catch most any problem. when an overcurrent or overrange condition exists for more than 8% of the time, this output becomes active. it is cleared when the problem occurs less than 2% of the time. undervoltage conditions immediately activate the fault output. it is active low and open drain to allow wire-oring. see cfault (pin 15) for additional information. 16 enable ringer output enable. active high. when enabled, the ring signal always starts immediately at 0 degrees. if amp00, sw1 and sw2 are held off when enable=0 but sw3 and sw4 continue switching. if amp=00, sw3 and sw4 are held off as well. when disabled, the error amplifer is set at unity gain to prevent saturation, reducing turn-on glitches when re-enabled. see syncmode (pin 13) for additional information. 17 off0 sets ring dc offset. offset changes are effected at the next phase crossing (0o/180o) of the ring signal. except for 00, offsets are set by the voltages at dcref1C3. (off0 is lsb) offset = ? x gain x (v dcrefx - v ref1 ) 00 = 0v 01 = dcref1 10 = dcref2 11 = dcref3 18 off1 19 amp0 sets ring amplitude. amplitude changes are effected at the next phase crossing (0o/180o) of the ring signal. amplitudes, as a percentage of full scale, are: (amp0 is lsb) full scale amplitude = 0.707v rms x gain 00 = 0% 01 = 50% 10 = 75% 11 = 100% 20 amp1 21 freq0 sets ring frequency. frequency changes are effected at the next phase crossing (0o/180o) of the ring signal. frequencies when using a 19.6608mhz crystal are: (freq0 is lsb) 000 = 16.7hz 001 = 20hz 010 = 25hz 011 = 30hz 100 = 33.3hz 101 = 40hz 110 = 50hz 111 = 60hz 22 freq1 23 freq2 24 le latch enable. the latch gates control inputs freq0C2, amp0C1, off0C1, and enable. when le is high, latch outputs follow inputs. on a lowCgoing transition, outputs are latched. 25 tdly an rc network on this pin sets the primary to secondary switch delay . this prevents the secondaryCside switches (sw3&4) from turning on prematurely. t dly = 0.48rc 26 tdb an rc network on this pin sets the deadband (breakCbeforeCmake time) on the primaryCside switches (sw1&2). deadband prevents both switches from conducting simultaneously . t db = 0.48rc 27 dgnd digital ground. connect to agnd and pgnd close to the ic. 28 sw4 secondaryCside switch driver output. 29 sw3 secondaryCside switch driver output. 30 sw2 primaryCside n-channel switch driver output. pin description (cont.) supertex inc. www .supertex.com
13 doc.# dsfp - hv461 c071913 hv461 pin name description 31 sw1 primaryCside p-channel switch driver output. 32 pgnd power ground. connect to agnd and dgnd close to the ic. 33 vgd supply for the sw1C4 drivers. an external boost converter controlled by vdr provides 9.6v for driving the power stage mosfets. an undervoltage condition on this supply pin disables ringer output and activates the fault output. 34 vdr gate drive for the external boost converter circuit. outputs a fxed 50% duty cycle at the ringer pwm frequency (see rosc, pin 9). output voltage regulation is via burp-mode operation. this output is boostrapped to vgd, thus during startup vdr amplitude is vdd and after startup is vgd. (see vgd, pin 33) 35 dvdd supply for the digital section. 3.0v to 3.6v input. undervoltage disables ringer output. must be from the same source as avdd. bypass with a 100nf capacitor to ground as close as possible to the ic. an undervoltage condition on this supply pin disables ringer output and activates the fault output. 36 cl+ current limit amplifer non-inverting input. 37 cl- current limit amplifer inverting input. 38 clcomp current limit compensation. an rc network connected between this pin and cl- establishes current limit reaction time and stability. 39 diffamp+ differential amplifer non-inverting input. the differential amplifer sets gain, establishing output amplitude and dc offset in conjunction with ampx and offx. gain = r fb2 /r fb1 (r fb3 = r fb1 and r fb4 = r fb2 , see schematic) 40 diffamp- differential amplifer inverting input. 41 diffampo differential amplifer output. 42 comp2 error amplifer compensation. an rc network connected between these pins establishes loop stability. 43 comp1 comp1 is the error amp inverting input. comp2 is the error amp output. 44 sineref sine wave reference. amplitude is 2v p-p nominal. output impedance is approximately 16k?. an external 33nf capacitor from this pin to ground should be employed to remove high frequency synthesizer ripple. synthesizer ripple is at a frequency of 2 15 f ring 45 agnd analog ground. connect to agnd and dgnd close to the ic. 46 vdcl voltage applied to this pin sets the min/max duty cycle limits. if the pwm controller hits these limits, clipping of the ringer output will occur and the fault output will be activated. d min = 0.4v dcl d max = 1 - 0.4v dcl 47 dcref1 in conjunction with the offx control inputs, voltages applied to these inputs set the output dc offset. output offset is the selected dcrefx voltage multiplied by gain. see also off0 & off1 (pins 17 & 18) 48 dcref2 pin description (cont.) supertex inc. www .supertex.com
14 hv461 (the package drawing(s) in this data sheet may not refect the most current specifcations. for the latest package outline information go to http://www.supertex.com/packaging.html .) doc.# dsfp - hv461 c071913 48-lead lqfp package outline (fg) 7.00x7.00mm body, 1.60mm height (max), 0.50mm pitch symbol a a1 a2 b d d1 e e1 e l l1 l2 dimension (mm) min 1.40* 0.05 1.35 0.17 8.80* 6.80* 8.80* 6.80* 0.50 bsc 0.45 1.00 ref 0.25 bsc 0 o nom - - 1.40 0.22 9.00 7.00 9.00 7.00 0.60 3.5 o max 1.60 0.15 1.45 0.27 9.20* 7.20* 9.20* 7.20* 0.75 7 o jedec registration ms-026, variation bbc, issue d, jan. 2001. * this dimension is not specifed in the jedec drawing. drawings are not to scale. supertex doc. #: dspd-48lqfpfg version, d041309. 1 seating plane gauge plane l l1 l2 vi ew b view b seating plane top view side view note 1 (index area d1/4 x e1/4) 48 a2 a a1 b d d1 e e1 e note: 1. a pin 1 identifer must be located in the index area indicated. the pin 1 identifer can be: a molded mark/identifer; an embedded metal marker; or a printed indicator. supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate ?product liability indemnification insurance agreement.? supertex inc. does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry and specifications are subject to change without notice. for the latest product specifications refer to the supertex inc. (website: http//www .supertex.com) ?2013 supertex inc. all rights reserved. unauthorized use or reproduction is prohibited. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com

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